integrated circuit systems, inc. ICS95V847 0718e?11/24/08 block diagram pll fb_int fb_inc clk_inc clk_int fb_outt fb_outc clkt0 clkt1 clkt2 clkt3 clkt4 clkc0 clkc1 clkc2 clkc3 clkc4 2.5v wide range frequency clock driver (45mhz - 233mhz) pin configuration 24-pin tssop recommended application: zero delay board fan out, so-dimm provides complete ddr registered dimm solution with icssstv16857, icssstv16859 or icssstv32852 product description/features: low skew, low jitter pll clock driver 1 to 5 differential clock distribution (sstl_2) feedback pins for input to output synchronization spread spectrum tolerant inputs switching characteristics: cycle - cycle jitter: <60ps output - output skew: <60ps period jitter: 30ps duty cycle: 49.5% - 50.5% functionality s t u p n is t u p t u o e t a t s l l p d d v at n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n gl hlhl h f f o / d e s s a p y b d n gh lhlh l f f o / d e s s a p y b v 5 . 2 ) m o n ( lhlhlh n o v 5 . 2 ) m o n ( hlhlhl n o 4.40 mm. body, 0.65 mm. pitch gnd clkc0 clkt0 gnd vdd clk_int clk_inc avdd agnd clkc1 clkt1 vdd clkt4 clkc4 clkc3 clkt3 vdd fb_int fb_inc fb_outc fb_outt clkt2 clkc2 gnd ICS95V847 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
2 ICS95V847 0718e?11/24/08 pin descriptions this pll clock buffer is designed for a v dd of 2.5v, an av dd of 2.5v and differential data input and output levels. ICS95V847 is a zero delay buffer that distributes a differential clock input pair (clk_int, clk_inc) to five differential pair of clock outputs (clkt[4:0], clkc[4:0]) and one differential pair feedback clock output (fb_out, fb_outc). the clock outputs are controlled by input clock (clk_int, clk_inc), the feedback clock (fb_int, fb_inc) and the analog power input (av dd ). when av dd is grounded, the pll is turned off and bypassed for test purposes. the pll in ICS95V847 clock driver uses the input clock (clk_inc, clk_int) and the feedback clock (fb_int, fb_inc) to provide high-performance, low-skew, low-jitter differential output clocks (clkt[4:0], clkc[4:0]). ICS95V847 is also able to track spread spectrum clock (ssc) for reduced emi. ICS95V847 is characterized for operation from 0c to 85c. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 0 2 , 2 1 , 5d d vr w pv 5 . 2 , y l p p u s r e w o p 3 1 , 4 , 1d n gr w pd n u o r g 8d d v ar w pv 5 . 2 , y l p p u s r e w o p g o l a n a 9d n g ar w pd n u o r g g o l a n a 4 2 , 1 2 , 5 1 , 1 1 , 3] 4 : 0 [ t k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " 3 2 , 2 2 , 4 1 , 0 1 , 2] 4 : 0 [ c k l ct u os t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " 6t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 7c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " 6 1t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a t n i _ b f 7 1c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s c n i _ b f o t 9 1t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 8 1c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f
3 ICS95V847 0718e?11/24/08 absolute maximum ratings supply voltage (vdd & avdd) . . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v dd + 0.5v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 148 ma i ddpd c l = 0pf 100 a high impedance output current i oz v dd = 2.7v, vout = v dd or gnd 10 ma input clamp voltage v ik v dd = 2.3v iin = -18ma -1.2 v i oh = -1 ma v dd - 0.1 v i oh = -12 ma 1.7v v i ol =1 ma 0.1 v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 2.5 3.5 pf 1 guaranteed by design at 233mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
4 ICS95V847 0718e?11/24/08 recommended operating condition (see note1) t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd , a vdd 2.3 2.5 2.7 v clkt, clkc, fb_inc 0.4 v dd /2 - 0.18 v pd# -0.3 0.7 v clkt, clkc, fb_inc v dd /2 + 0.18 2.1 v pd# 1.7 v dd + 0.6 v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v dc - clkt, fb_int 0.36 v dd + 0.6 v ac - clkt, fb_int 0.7 v dd + 0.6 v output differential cross- voltage (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v input differential cross- voltage (note 4) v ix v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v high level output current i oh -6.4 ma low level output current i ol 5.5 ma operating free-air temperature t a 085c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal must be crossing.
5 ICS95V847 0718e?11/24/08 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 85c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+ 0.2v @ 25 o c 45 233 mhz application frequency range freq app 2.5v+ 0.2v @ 25 o c 95 210 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics (see note 3) parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 clk_in to any output 5.5 ns high-to low level propagation delay time t pll 1 clk_in to any output 5.5 ns output enable time t en pd# to any output 5 ns output disable time tdis pd# to any output 5 ns period jitter t jit (per) 100mhz to 200mhz -30 30 ps half-period jitter t(jit_hper) 100mhz to 200mhz -75 30 ps input clock slew rate t sl(i) 14v/ns output clock slew rate t sl(o) 12.5v/ns cycle to cycle jitter 1 t cyc -t cyc 100mhz to 200mhz 60 ps phase error t (phase error) 4 -50 0 50 ps output to output skew t skew 60 ps
6 ICS95V847 0718e?11/24/08 gnd ICS95V847 v dd v dd /2 v (clkc) v (clkc) scope c=14p f -vdd/2 -vdd/2 -vdd/2 vdd/2 z=60 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? r=50 ? r=60 ? r=60 ? r=50 ? v (tt) v (tt) c=14pf note: v (tt) = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fboutc x y , fboutt x parameter measurement information ICS95V847 figure 3. cycle-to-cycle jitter
7 ICS95V847 0718e?11/24/08 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (sk_o) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) c(n) 1 f o figure 6. period jitter
8 ICS95V847 0718e?11/24/08 clock inputs and outputs 80% 20% 80% 20% rise t sl fall t sl v id ,v od figure 8. input and output slew rates parameter measurement information t (hper_n) t (hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t =- (jit_hper) t (jit_hper_n) 1 2xf o
9 ICS95V847 0718e?11/24/08 ordering information 95v847 y glf-t 4.40 mm. body, 0.65 mm. pitch tssop (173 mil) (0.0256 inch) index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 24 7.70 7.90 .303 .311 10-0035 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.65 basic 0.0256 basic see variations see variations see variations see variations 6.40 basic 0.252 basic symbol in millimeters in inches common dimensions common dimensions example: xxxx y g lf- t designation for tape and reel packaging annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type
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